FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 2,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, IDE, serial and
parallel ports, Bank 2 of the RTC registers,
auxiliary I/O and ACCESS.bus can be moved
via the configuration registers. Some addresses
are used to access more than one register.
The host processor communicates with the
FDC37C93xFR through a series of read/write
registers. The port addresses for these registers
are shown in Table 2. Register access is
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide except
the IDE data register at port 1F0H which is 16
bits wide. All host interface output buffers are
capable of sinking a minimum of 12 mA.
Table 2 - Super I/O Block Addresses
LOGICAL
DEVICE
0
ADDRESS
Base+(0-5) and +(7)
BLOCK NAME
Floppy Disk
NOTES
Base+(0-7)
Serial Port Com 1
Serial Port Com 2
4
5
Base1+(0-7)
Base2+(0-7)
IR Support
Fast IR
Parallel Port
SPP
3
Base+(0-3)
Base+(0-7)
EPP
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
ECP
ECP+EPP+SPP
Base1+(0-7), Base2+(0)
Base1+(0-7), Base2+(0)
IDE 1
IDE 2
RTC
1
2
6
70, 71
Base2+(0,1)
60, 64
KYBD
7
8
Base1+(0)
Base2+(0)
Aux. I/O
GPR
GPW
Base+(0-3)
ACCESS.bus
9
Note 1: Refer to the configuration register descriptions for setting the base address
14
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