INTEGRATED DRIVE ELECTRONICS INTERFACE
The FDC37C93xFR contains two IDE interfaces.
AT Host. There are two groups of registers,
the AT Task File, and the Miscellaneous AT
Register.
This enables hard disks with embedded
controllers (AT or IDE) to be interfaced to the
host processor. The IDE interface performs the
address decoding for the IDE interface,
generates the buffer enables for external buffers
and provides internal buffers for the low byte
IDE data transfers. For more information, refer
to the IDE pin descriptions and the ATA
specification. The following example uses IDE1
ADDRESS 1F0H-1F7H; 170H-177H
These AT registers contain the Task File
Registers. These registers communicate data,
command, and status information with the AT
host, and are addressed when nHCS0 or nHCS2
is low.
base1=1F0H,
base2=3F6H
and
IDE2
base1=170H, base2 =376H.
ADDRESS 3F6H/376H;
These AT registers may be used by the BIOS for
drive control. They are accessed by the AT
interface when nHCS1 or nHCS3 is active low.
HOST FILE REGISTERS
The Host File Registers are accessed by the
FIGURE 2 - HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE)
PRIMARY SECONDARY
1F0H 1F0H
TASK FILE REGISTERS
|
|
1F7H
177H
3F6H
376H
MISC. AT REGISTERS
task file registers are
ATA
and EATA
compatible. Please refer to the ATA and EATA
specifications. These are available from:
TASK FILE REGISTERS
Task File Registers may be accessed by the
host AT when pin nHDCS0 is active (low). The
Data Register (1F0H) is 16 bits wide; the
remaining task file registers are 8 bits wide. The
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