cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit
implementation. (PWord = 1 byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 7 compress
This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE
compression. It does support hardware de-compression!
BIT 6 intrValue
Returns the value on the ISA iRq line to determine possible conflicts.
BITS 2:0 DMA Software Select
The DMA Software Select bits indicate the DMA channel number that has been allocated to the Parallel Port. The
channel encoding is shown in Table 66. The DMA Software select bits shadow the ECP DMA Select bits in the ECP
Software Select register CR22.
Table 66 - DMA Software Select Encoding
DMA Software
Select
(cnfgB)
DMA
SELECTED
D2 D1 D0
3
2
1
0
0
0
0
1
1
0
0
1
0
1
0
Other
BITS 5:3 IRQ Software Select
The IRQ Software Select bits indicate the IRQ channel number that has been allocated to the Parallel Port. The IRQ
encoding is shown in Table 67. The IRQ Software select bits shadow the ECP IRQ Select bits in the ECP Software
Select register CR22.
Table 67 - IRQ Software Select Encoding
IRQ Software
Select
(cnfgB)
IRQ
SELECTED
D5 D4 D3
15
14
11
10
9
7
5
1
1
1
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
0
1
0
1
1
0
Other
SMSC DS – FDC37N3869
Page 82
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
