Configure............................................................................................................................................51
Version ...............................................................................................................................................52
Relative Seek .......................................................................................................................................52
Perpendicular Mode............................................................................................................................52
LOCK..................................................................................................................................................53
ENHANCED DUMPREG .......................................................................................................................54
COMPATIBILITY......................................................................................................................................54
PARALLEL PORT FLOPPY DISK CONTROLLER ....................................................................................................54
SERIAL PORT (UART).................................................................................................................................56
REGISTER DESCRIPTION...............................................................................................................................56
RECEIVE BUFFER REGISTER (RB) .....................................................................................................56
TRANSMIT BUFFER REGISTER (TB) ...................................................................................................56
INTERRUPT ENABLE REGISTER (IER) ................................................................................................56
INTERRUPT IDENTIFICATION REGISTER (IIR).....................................................................................57
FIFO CONTROL REGISTER (FCR) .......................................................................................................58
LINE CONTROL REGISTER (LCR) .......................................................................................................59
MODEM CONTROL REGISTER (MCR)..................................................................................................60
LINE STATUS REGISTER (LSR)...........................................................................................................61
MODEM STATUS REGISTER (MSR).....................................................................................................62
SCRATCHPAD REGISTER (SCR) .........................................................................................................62
PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES ......................................................63
The Affects of RESET on the UART Registers .....................................................................................63
FIFO INTERRUPT MODE OPERATION...............................................................................................................64
FIFO POLLED MODE OPERATION...................................................................................................................64
NOTES ON SERIAL PORT FIFO MODE OPERATION ............................................................................................66
GENERAL ...........................................................................................................................................66
TX AND RX FIFO OPERATION.............................................................................................................66
INFRARED INTERFACE ..............................................................................................................................67
IRDA SIR/FIR AND ASKIR ..........................................................................................................................67
CONSUMER IR............................................................................................................................................67
HARDWARE INTERFACE ................................................................................................................................68
IR HALF DUPLEX TURNAROUND DELAY TIME ....................................................................................................69
PARALLEL PORT....................................................................................................................................70
IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES.................................................................71
DATA PORT ........................................................................................................................................71
STATUS PORT ....................................................................................................................................71
CONTROL PORT .................................................................................................................................72
EPP ADDRESS PORT..........................................................................................................................72
EPP DATA PORT 0..............................................................................................................................73
EPP DATA PORT 1..............................................................................................................................73
EPP DATA PORT 2..............................................................................................................................73
EPP DATA PORT 3..............................................................................................................................73
EPP 1.9 OPERATION...............................................................................................................................73
Software Constraints ..........................................................................................................................73
EPP 1.9 Write ......................................................................................................................................73
EPP 1.9 Read ......................................................................................................................................74
EPP 1.7 OPERATION...............................................................................................................................75
Software Constraints ..........................................................................................................................75
EPP 1.7 Write ......................................................................................................................................75
EPP 1.7 Read ......................................................................................................................................75
EXTENDED CAPABILITIES PARALLEL PORT...........................................................................................77
Vocabulary..........................................................................................................................................77
ISA IMPLEMENTATION STANDARD ....................................................................................................78
Description .........................................................................................................................................78
Register Definitions ............................................................................................................................78
SMSC DS – FDC37N3869
Page 5
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
