CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 3.3V
Table 121 - Clock Pin Loading
LIMITS
TYP
PARAMETER
Clock Input Capacitance
Input Capacitance
SYMBOL
CIN
CIN
COUT
MIN
MAX
20
10
UNIT
pF
pF
TEST CONDITION
All pins except pin
under test tied to AC
ground
Output Capacitance
20
pF
Table 122 - Capacitive Loading per Output Pin
SIGNAL NAME
SD[0:7]
IOCHRDY
IRQs
TOTAL CAPACITANCE (pF)
240
240
120
120
240
240
240
240
240
240
240
240
100
100
100
240
240
240
240
240
DRQs
nWGATE
nWDATA
nHDSEL
nDIR
nSTEP
nDS[1:0]
nMTR[1:0]
DRVDEN[1:0]
TXD
nRTS
nDTR
PD[7:0]
nSLCTIN
nINIT
nALF
nSTB
SMSC DS – FDC37N3869
Page 116
Rev. 10/25/2000
SMSC [ SMSC CORPORATION ]
