Table 35 - Register Summary for an Individual UART Channel (continued)
BIT 2
Data Bit 2
Data Bit 2
BIT 3
Data Bit 3
Data Bit 3
BIT 4
Data Bit 4
Data Bit 4
0
BIT 5
Data Bit 5
Data Bit 5
0
BIT 6
Data Bit 6
Data Bit 6
0
BIT 7
Data Bit 7
Data Bit 7
0
Enable
Receiver Line
Status
Enable
MODEM
Status
Interrupt
(ELSI)
Interrupt
(EMSI)
FIFOs
Enabled
(Note 5)
Interrupt ID
Bit
Interrupt ID
Bit (Note 5)
0
0
FIFOs
Enabled
(Note 5)
XMIT FIFO
Reset
DMA Mode
Select (Note
6)
Reserved
Reserved
Stick Parity
RCVR Trigger RCVR Trigger
LSB
MSB
Divisor Latch
Access Bit
(DLAB)
Number of
Stop Bits
(STB)
Parity Enable Even Parity
(PEN)
Set Break
Select (EPS)
OUT1
OUT2
Loop
0
0
0
(Note 3)
(Note 3)
Parity Error
(PE)
Framing Error Break
(FE)
Transmitter
Interrupt (BI) Holding
Transmitter
Empty
(TEMT)
Error in
RCVR FIFO
(Note 5)
Register
(THRE)
(Note 2)
Data Carrier
Detect (DCD)
Trailing Edge Delta Data
Ring Indicator Carrier Detect (CTS)
Clear to Send Data Set
Ring Indicator
Ready (DSR) (RI)
(TERI)
(DDCD)
Bit 2
Bit 3
Bit 4
Bit 4
Bit 12
Bit 5
Bit 5
Bit 13
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
Bit 2
Bit 3
Bit 10
Bit 11
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow
Register (LD8:CRC3[7:0]) and UART2 FIFO Control Shadow Register (LD8:CRC4[7:0]).
78
SMSC [ SMSC CORPORATION ]
