received data available interrupt; XMIT FIFO
empty has the same priority as the current
transmitter holding register empty interrupt.
·
·
Bit 0=1 as long as there is one byte in the
RCVR FIFO.
Bits 1 to 4 specify which error(s) have
occurred. Character error status is handled
the same way as when in the interrupt
mode, the IIR is not affected since EIR bit
Bit 5 indicates when the XMIT FIFO is
empty.
Bit 6 indicates that both the XMIT FIFO and
shift register are empty.
Bit 7 indicates whether there are any errors
in the RCVR FIFO.
FIFO POLLED MODE OPERATION
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or
3 or all to zero puts the UART in the FIFO
Polled Mode of operation. Since the RCVR and
XMITTER are controlled separately, either one
or both can be in the polled mode of operation.
In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
·
·
·
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFOs are still
fully capable of holding characters.
Table 33 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432 MHz Clock
for 115.2k ; Using 3.6864 MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k
DESIRED
DIVISOR USED TO
PERCENT ERROR DIFFERENCE
CRxx:
BAUD RATE
GENERATE 16X CLOCK
BETWEEN DESIRED AND ACTUAL*
BIT 7 OR 6
50
75
2304
1536
1047
857
768
384
192
96
0.001
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
110
-
134.5
150
0.004
-
300
-
600
-
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
-
64
-
58
0.005
48
-
32
-
24
-
16
-
12
-
-
6
3
0.030
0.16
2
75
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