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FDC37C669_07 参数 Datasheet PDF下载

FDC37C669_07图片预览
型号: FDC37C669_07
PDF下载: 下载PDF文件 查看货源
内容描述: 98/99 PC兼容的超级I / O软盘控制器,红外支持 [PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support]
分类和应用: 控制器PC
文件页数/大小: 164 页 / 575 K
品牌: SMSC [ SMSC CORPORATION ]
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When both GAP and WGATE bits of the  
PERPENDICULAR MODE COMMAND are both  
programmed to "0" (Conventional mode), then  
D0, D1, D2, D3, and D4 can be programmed  
independently to "1" for that drive to be set  
automatically to Perpendicular mode. In this  
mode the following set of conditions also apply:  
1. The GAP2 written to a perpendicular drive  
during a write operation will depend upon the  
programmed data rate.  
Note: Bits D0-D3 can only be overwritten when  
OW is programmed as a "1".  
If either GAP or WGATE is a "1" then  
D0-D3 are ignored.  
Software and hardware resets have the  
following effect on the PERPENDICULAR  
MODE COMMAND:  
1. "Software" resets (via the DOR or DSR  
registers) will only clear GAP and WGATE  
bits to "0". D0-D3 are unaffected and retain  
their previous value.  
2. The write pre-compensation given to  
perpendicular mode drive wil be 0ns.  
a
3. For D0-D3 programmed to "0" for  
conventional mode drives any data written  
will be at the currently programmed write  
pre-compensation.  
2. "Hardware" resets will clear all bits (GAP,  
WGATE and D0-D3) to "0", i.e all  
conventional mode.  
Table 29 - Effects of WGATE and GAP Bits  
PORTION OF  
GAP 2  
LENGTH OF  
WRITTEN BY  
GAP2 FORMAT WRITE DATA  
WGATE GAP  
MODE  
FIELD  
OPERATION  
0
0
0
1
Conventional  
Perpendicular  
(500 Kbps)  
Reserved  
(Conventional)  
Perpendicular  
(1 Mbps)  
22 Bytes  
22 Bytes  
0 Bytes  
19 Bytes  
1
1
0
1
22 Bytes  
41 Bytes  
0 Bytes  
38 Bytes  
The LOCK command defines whether the  
EFIFO, FIFOTHR, and PRETRK parameters of  
the CONFIGURE command can be RESET by  
the DOR and DSR registers. When the LOCK  
bit is set to logic "1" all subsequent "software  
RESETS by the DOR and DSR registers will not  
change the previously set parameters to their  
default values. All "hardware" RESET from the  
RESET pin will set the LOCK bit to logic "0" and  
return the EFIFO, FIFOTHR, and PRETRK to  
LOCK  
In order to protect systems with long DMA  
latencies against older application software that  
can disable the FIFO the LOCK Command has  
been added. This command should only be  
used by the FDC routines, and application  
software should refrain from using it. If an  
application calls for the FIFO to be disabled  
then the CONFIGURE command should be  
used.  
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