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FDC37C669-MT 参数 Datasheet PDF下载

FDC37C669-MT图片预览
型号: FDC37C669-MT
PDF下载: 下载PDF文件 查看货源
内容描述: [Floppy Disk Drive, 0.25MBps, IDE Compatible, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100]
分类和应用: 数据传输PC驱动外围集成电路驱动器
文件页数/大小: 162 页 / 617 K
品牌: SMSC [ SMSC CORPORATION ]
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DESCRIPTION OF PIN FUNCTIONS  
BUFFER  
QFP/  
TQFP  
PIN NO.  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
81,91  
nRequest to  
Send  
nRTS1  
O4  
Active low Request to Send outputs for the  
Serial Port. Handshake output signal notifies  
modem that the UART is ready to transmit  
data. This signal can be programmed by  
writing to bit 1 of Modem Control Register  
(MCR). The hardware reset will reset the  
nRTS signal to inactive mode (high). Forced  
inactive during loop mode operation.  
nRTS2  
(SYSOPT)  
(System Option)  
At the trailing edge of hardware reset, the  
nRTS2 input is latched to determine the  
configuration base address.  
0 : INDEX Base I/O Address = 3F0 Hex  
1 : INDEX Base I/O Address = 370 Hex  
83,93  
nData Terminal  
Ready  
nDTR1  
nDTR2  
O4  
Active low Data Terminal Ready outputs for  
the serial port. Handshake output signal  
notifies modem that the UART is ready to  
establish data communication link. This signal  
can be programmed by writing to bit 0 of  
Modem Control Register (MCR).  
The  
hardware reset will reset the nDTR signal to  
inactive mode (high). Forced inactive during  
loop mode operation.  
82,92  
nClear to Send  
nCTS1  
nCTS2  
I
Active low Clear to Send inputs for the serial  
port. Handshake signal which notifies the  
UART that the modem is ready to receive  
data. The CPU can monitor the status of  
nCTS signal by reading bit 4 of Modem Status  
Register (MSR). A nCTS signal state change  
from low to high after the last MSR read will  
set MSR bit 0 to a 1. If bit 3 of Interrupt  
Enable Register is set, the interrupt is  
generated when nCTS changes state. The  
nCTS signal has no effect on the transmitter.  
Note: Bit 4 of MSR is the complement of  
nCTS.  
9
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