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FDC37C669-MT 参数 Datasheet PDF下载

FDC37C669-MT图片预览
型号: FDC37C669-MT
PDF下载: 下载PDF文件 查看货源
内容描述: [Floppy Disk Drive, 0.25MBps, IDE Compatible, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100]
分类和应用: 数据传输PC驱动外围集成电路驱动器
文件页数/大小: 162 页 / 617 K
品牌: SMSC [ SMSC CORPORATION ]
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DESCRIPTION OF PIN FUNCTIONS  
BUFFER  
QFP/  
TQFP  
PIN NO.  
TYPE  
NAME  
SYMBOL  
DESCRIPTION  
80,90  
nData Set Ready nDSR1  
I
Active low Data Set Ready inputs for the serial  
port. Handshake signal which notifies the  
UART that the modem is ready to establish  
nDSR2  
the communication link.  
monitor the status of nDSR signal by reading  
bit 5 of Modem Status Register (MSR).  
The CPU can  
A
nDSR signal state change from low to high  
after the last MSR read will set MSR bit 1 to a  
1. If bit 3 of Interrupt Enable Register is set,  
the interrupt is generated when nDSR  
changes state. Note: Bit 5 of MSR is the  
complement of nDSR.  
85,87  
nData Carrier  
Detect  
nDCD1  
nDCD2  
I
Active low Data Carrier Detect inputs for the  
serial port. Handshake signal which notifies  
the UART that carrier signal is detected by the  
modem. The CPU can monitor the status of  
nDCD signal by reading bit 7 of Modem Status  
Register (MSR). A nDCD signal state change  
from low to high after the last MSR read will  
set MSR bit 3 to a 1. If bit 3 of Interrupt  
Enable Register is set, the interrupt is  
generated when nDCD changes state. Note:  
Bit 7 of MSR is the complement of nDCD.  
84,86  
nRing Indicator  
nRI1  
nRI2  
I
Active low Ring Indicator inputs for the serial  
port. Handshake signal which notifies the  
UART that the telephone ring signal is  
detected by the modem. The CPU can  
monitor the status of nRI signal by reading bit  
6 of Modem Status Register (MSR). A nRI  
signal state change from low to high after the  
last MSR read will set MSR bit 2 to a 1. If bit 3  
of Interrupt Enable Register is set, the  
interrupt is generated when nRI changes  
state. Note: Bit 6 of MSR is the complement  
of nRI.  
PARALLEL PORT INTERFACE  
10