SERIAL PORT (UART)
The FDC37C669 incorporates two full function UARTs.
information on disabling, power down and changing the
base address of the UARTs. The interrupt from a UART
is enabled by programming OUT2 of that UART to a logic
"1". OUT2 being a logic "0" disables that UART's
interrupt.
They are compatible with the NS16450, the 16450 ACE
registers and the NS16550A. The UARTs perform
serial-to-parallel conversion on received characters and
parallel-to-serial conversion on transmit characters. The
data rates are independently programmable from 115.2K
baud down to 50 baud. The character options are
programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd,
sticky or no parity; and prioritized interrupts. The UARTs
each contain a programmable baud rate generator that is
capable of dividing the input clock or crystal by a number
from 1 to 65535. The UARTs are also capable of
supporting the MIDI data rate. Refer to the FDC37C669
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial Port is
shown below. The base addresses of the serial ports are
defined by the configuration registers (see Configuration
section).
The Serial Port registers are located at
sequentially increasing addresses above these base
addresses. The FDC37C669 contains two serial ports,
each of which contain a register set as described below.
Configuration
Registers
for
Table 31 - Addressing the Serial Port
DLAB*
A2
0
0
0
0
0
0
1
1
1
1
0
0
A1
0
0
0
1
1
1
0
0
1
1
0
0
A0
0
0
1
0
0
1
0
1
0
1
0
1
REGISTER NAME
0
0
Receive Buffer (read)
Transmit Buffer (write)
0
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
X
X
X
X
X
X
X
1
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write)
1
*NOTE: DLAB is Bit 7 of the Line Control Register
72
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