DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7
6
5
4
3
2
1
0
DSK
CHG
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 - 6 UNDEFINED
BIT 7 DSKCHG
The data bus outputs D0 - 6 will remain in a high
impedance state during a read of this register.
This bit monitors the pin of the same name and reflects
the opposite value seen on the disk cable.
PS/2 Mode
7
6
1
5
1
4
1
3
1
2
1
0
DSK
CHG
DRATE DRATE HIGH
SEL1
SEL0 DENS
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
BIT 0 nHIGH DENS
software reset, and are set to 250 Kbps after a hardware
reset.
This bit is low whenever the 500 Kbps or 1 Mbps data
rates are selected, and high when 250 Kbps and 300
Kbps are selected.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy controller.
See Table 13 for the settings corresponding to the
individual data rates. The data rate select bits are
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects
the opposite value seen on the disk cable.
unaffected
by
a
31
SMSC [ SMSC CORPORATION ]
