CR08
CR09
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 08H.
The default value of this register after power up is 00H.
This is the lower 4 bits (ADRA7:4) for the ADRx address
decode. The non-programmable address bits 3:0
default to 0000b.
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 09H. The
default value of this register after power up is 00H. This
is the upper 3 bits (ADRA10:8) (D2 - MSB, D0 - LSB) for
the ADRx address decode. ADRx Config (bits 7:6) define
the configuration of the ADRx decoder as follows:
D7
0
D6
0
ADRx Configuration
ADRx disabled
0
1
1 Byte decode
A[3:0]=0000b
1
1
0
1
8 Byte block decode
A[3:0]=0XXXb
16 byte block decode
A[3:0]=XXXXb
Upper Address Decode requirements : nCS='0' is required to qualify the ADRx output.
CR0A
register after power up is 00H. This byte defines the
FIFO threshold for the ECP mode parallel port.
This register can only be accessed in the Configuration
Mode and after the CSR has been initialized to 0AH. The
default
value
of
this
Table 54 - CR0A
D7
D6
D5
D4
D3
D2
ECP F I F O T H R E S H O L D
THR2 THR1
D1
D0
RESERVED - READ ONLY 0 HEX
THR3
THR0
CR0B
this register after power up is 00H. This register indicates
the data rate table used for each drive. Refer to CR1F for
Drive Type register.
This register can only be ac1cessed in the Configuration
Mode and after the CSR has been initialized to
0BH.
The
default
value
of
Table 55 - CR0B
FDD1
FDD3
FDD2
FDD0
D7
DRT1
D6
D5
D4
D3
D2
D1
D0
DRT0
DRT1
DRT0
DRT1
DRT0
DRT1
DRT0
126
SMSC [ SMSC CORPORATION ]
