UART Power Management
Parallel Port
Direct power management is controlled by CR2 bits 3 and
7. Refer to CR2 bits 3 and 7 for more information.
Direct power management is controlled by CR1 bit 2.
Refer to CR1 bit 2 for more information.
Auto Power Management is enabled by CR7 bits 5 and 6.
When set, these bit allows the following auto power
management operations:
Auto Power Management is enabled by CR7 bit 4. When
set, this bit allows the ECP or EPP logical parallel port
blocks to be placed into powerdown when not being used.
1. The transmitter enters auto powerdown when the
transmit buffer and shift register are empty.
The EPP logic is in powerdown under any of the following
conditions:
2. The receiver enters powerdown when the following
conditions are all met:
1. EPP is not enabled in the configuration registers.
2. EPP is not selected through ecr while in ECP mode.
a. Receive FIFO is empty
b. The receiver is waiting for a start bit.
The ECP logic is in powerdown under any of the following
conditions:
Note:
While in powerdown the Ring Indicator interrupt
is still valid and transitions when the RI input
changes.
1. ECP is not enabled in the configuration registers.
2
SPP, PS/2 Parallel port or EPP mode is selected
through ecr while in ECP mode.
Exit Auto Powerdown
The transmitter exits powerdown on a write to the XMIT
buffer. The receiver exits auto powerdown when RXDx
changes state.
Exit Auto Powerdown
The parallel port logic can change powerdown modes
when the ECP mode is changed through the ecr register
or when the parallel port mode is changed through the
configuration registers.
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