TABLE 79 - UART INTERRUPT OPERATION
UART2
UART1
IRQ PINS
UART1
OUT2 bit
UART1
UART2
UART2
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IRQ
UART1
Pin State
UART2
IRQ State
OUT2 bit
IRQ State
Pin State
Bit
This part of the table is based on the assumption that both UARTS have selected different IRQ
pins
0
1
1
0
0
1
1
1
1
0
1
1
0
0
1
1
1
1
Z
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
Z
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
Z
1
0
Z
Z
1
1
0
0
Z
1
0
1
0
1
1
1
0
Z
Z
Z
1
0
1
0
1
0
Z
1
0
1
0
1
1
1
0
asserted
de-asserted
Z
Z
Z
asserted
de-asserted
asserted
de-asserted
asserted
de-asserted
Z
Z
asserted
asserted
de-asserted
de-asserted
Z
asserted
de-asserted
Z
Z
Z
asserted
de-asserted
asserted
de-asserted
asserted
de-asserted
Z
asserted
asserted
de-asserted
de-asserted
It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ
number. However, if they are set to the same number then no damage to the chip will result.
190
SMSC [ SMSC CORPORATION ]
