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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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DMA Channel Select Configuration Register  
TABLE 75 - DMA CHANNEL SELECT CONFIGURATION REGISTER DESCRIPTION  
NAME  
REG INDEX  
DEFINITION  
STATE  
DMA Channel  
Select  
0x74 (R/W)  
Bits[2:0] select the DMA Channel.  
0x00=DMA0  
C
0x01=DMA1  
0x02=DMA2  
0x03=DMA3  
0x04-0x07= No DMA active  
Default = 0x04  
on Vcc POR or  
Reset_Drv  
Note: A DMA channel is activated by setting the DMA Channel Select register to [0x00-0x03] AND :  
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.  
for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.  
for the UART 2 logical device, by setting the DMA Enable bit. Refer to the IRCC specification.  
Note:DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.  
Note A. Logical Device IRQ and DMA Operation  
1) IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a  
register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the  
IRQ and DACK disabled by the Configuration Registers (active bit or address not valid).  
2) FDC: For the following cases, the IRQ and DACK used by the FDC are disabled (high impedance).  
Will not respond to the DREQ.  
a) Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".  
b) The FDC is in power down (disabled).  
3) Serial Port 1 and 2: Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the  
serial port interrupt is forced to a high impedance state - disabled.  
4) Parallel Port: SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled  
(high impedance).  
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