FUNCTIONAL DESCRIPTION
SUPER I/O REGISTERS
HOST PROCESSOR INTERFACE
The address map, shown below in Table 4, shows
the addresses of the different blocks of the Super
The host processor communicates with the
FDC37B78x through
registers. The port addresses for these registers
are shown in Table 4. Register access is
a series of read/write
I/O immediately after power up.
The base
addresses of the FDC, serial and parallel ports can
be moved via the configuration registers. Some
addresses are used to access more than one
register.
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide. All host
interface output buffers are capable of sinking a
minimum of 12 mA.
TABLE 3 - SUPER I/O BLOCK ADDRESSES
LOGICAL
ADDRESS
BLOCK NAME
DEVICE
NOTES
Base+(0-5) and +(7)
Floppy Disk
Parallel Port
SPP
0
3
Base+(0-3)
Base+(0-7)
EPP
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base+(0-7)
ECP
ECP+EPP+SPP
Serial Port Com 1
Serial Port Com 2
4
5
Base1+(0-7)
IR Support
Base2+(0-7)
Consumer IR
70,71, Base, Base+(1)
60, 64
Base + (0-17h)
Base + (0-1)
RTC
KYBD
ACPI, PME, SMI
Configuration
6
7
A
Note 1: Refer to the configuration register descriptions for setting the base address.
14
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