GENERAL PURPOSE I/O PINS
TABLE 2 - GENERAL PURPOSE I/O PIN FUNCTIONS
PIN NO.
QFP
DEFAULT
FUNCT
ALT
ALT
ALT
BUFFER
TYPE
INDEX
REGISTE
R
FUNCT 1 FUNCT 2 FUNCT 3
GPIO
77
78
79
80
81
82
4
6
39
2
91
92
83
84
85
86
87
88
89
90
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
nMTR1
nDS1
PCI_CLK
DRVDEN1
nROMCS2
nROMOE2
RD02,3
RD12,3
RD22,3
RD32,3
RD42,3
RD52,3
RD62,3
RD72,3
nSMI
nRING
WDT
-
-
-
IO12
IO4
IO4
IO24
IO4
GP1
GP1
GP1
GP1
GP1
GP1
GP1
GP1
GP5
GP5
GP5
GP5
GP6
GP6
GP6
GP6
GP6
GP6
GP6
GP6
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP50
GP52
GP53
GP54
GP60
GP61
GP62
GP63
GP64
GP65
GP66
GP67
EETI1
P17
-
EETI1
LED
-
-
-
-
-
-
IRRX2
IRTX2
GPIO
GPIO
IRQ14
GPIO
IRQ11
IRQ12
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ10
-
-
-
-
IO24
IO24
IO24
IO12
IO24
IO12
IO12
IO12
IO24
IO12
IO12
IO12
IO12
IO12
IO12
GPIO
IRQ8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
nSMI
EETI1
EETI1
nSMI
LED
nRING
WDT
P17
-
-
-
Note 1 Either Edge Triggered Interrupt Inputs.
Note 2 At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for alternate
functions, nROMCS must stay high until those pins are finished being programmed.
Note 3 These pins cannot be programmed as open drain pins in their original function.
REFERENCE DOCUMENTS
SMSC Consumer Infrared Communications Controller (CIrCC) V1.X
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.
Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.
PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.
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SMSC [ SMSC CORPORATION ]
