DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL1 SPEED BIT2
0.16
HIGH
460800
32769
1
Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note 2: The High Speed bit is located in the Device Configuration Space.
Table 32 - Reset Function Table
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
RESET CONTROL
RESET
RESET STATE
All bits low
RESET
Bit 0 is high; Bits 1 - 7 low
All bits low
RESET
Line Control Reg.
RESET
All bits low
MODEM Control Reg.
Line Status Reg.
RESET
All bits low
RESET
All bits low except 5, 6 high
MODEM Status Reg.
TXD1, TXD2
RESET
Bits 0 - 3 low; Bits 4 - 7 input
RESET
High
INTRPT (RCVR errs)
RESET/Read LSR
Low
INTRPT (RCVR Data Ready) RESET/Read RBR
Low
INTRPT (THRE)
OUT2B
RESET/ReadIIR/Write THR
Low
RESET
RESET
RESET
RESET
High
RTSB
High
DTRB
High
OUT1B
High
RCVR FIFO
RESET/
All Bits Low
FCR1*FCR0/_FCR0
XMIT FIFO
RESET/
All Bits Low
FCR1*FCR0/_FCR0
76
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