TABLE 92 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE TIMING
NAME
DESCRIPTION
nIOW Asserted to PDATA Valid
nWAIT Asserted to nWRITE Change (Note 1)
nWRITE to Command Asserted
nWAIT Deasserted to Command Deasserted
(Note 1)
MIN
0
60
5
TYP
MAX
50
185
35
UNITS
ns
ns
ns
ns
t1
t2
t3
t4
60
190
t5
t6
t7
t8
t9
nWAIT Asserted to PDATA Invalid (Note 1)
Time Out
Command Deasserted to nWAIT Asserted
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
(Note 1)
0
10
0
10
0
ns
μs
ns
ns
ns
ns
ns
12
t10
t11
0
60
24
160
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
nWAIT Asserted to Command Asserted (Note 1)
Command Asserted to nWAIT Deasserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
10
0
60
0
10
40
10
40
60
0
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
70
210
10
nIOW Asserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to nWRITE Asserted (Note 1)
nWAIT Asserted to PDIR Low
185
PDIR Low to nWRITE Asserted
0
Note 1: nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered
to have settled after it does not transition for a minimum of 50 nsec.
222
SMSC [ SMSC CORPORATION ]
