TABLE 87 - SINGLE TRANSFER DMA TIMING
NAME
t1
t2
t3
t4
t5
t6
t7
t8
DESCRIPTION
nDACK Delay Time from FDRQ High
DRQ Reset Delay from nIOR or nIOW
FDRQ Reset Delay from nDACK Low
nDACK Width
nIOR Delay from FDRQ High
nIOW Delay from FDRQ High
Data Access Time from nIOR Low
Data Set Up Time to nIOW High
Data to Float Delay from nIOR High
Data Hold Time from nIOW High
nDACK Set Up to nIOW/nIOR Low
nDACK Hold after nIOW/nIOR High
TC Pulse Width
MIN
0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
100
150
0
0
100
60
40
10
10
5
10
60
40
10
t9
t10
t11
t12
t13
t14
t15
t16
AEN Set Up to nIOR/nIOW
AEN Hold from nDACK
TC Active to PDRQ Inactive
100
215
SMSC [ SMSC CORPORATION ]
