CLOCK TIMING
t2
t2
CLOCKI
FIGURE 17 - INPUT CLOCK TIMING
TABLE 85 - INPUT CLOCK TIMING
NAME
DESCRIPTION
MIN
TYP
70
35
31.25
16.53
MAX
UNITS
ns
ns
μs
μs
t1
t2
t1
t2
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
5
ns
t4
RESET_DRV
FIGURE 18 - RESET TIMING
TABLE 86 - RESET TIMING
DESCRIPTION
RESET width (Note 1)
NAME
t4
MIN
1.5
TYP MAX
UNITS
s
Note 1: The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
213