NAME
WDT_CFG
REG INDEX
DEFINITION
Watch-dog timer Configuration
Bit[0] Joy-stick Enable
STATE
0xF3
C
Default = 0x00
=1
WDT is reset upon an I/O read or write of the
Game Port
On VTR POR
=0
WDT is not affected by I/O reads or writes to
the Game Port.
Bits[0,2-7] are also
cleared on VCC POR
or RESET_DRV
Bit[1] Keyboard Enable
=1
=0
WDT is reset upon a Keyboard interrupt.
WDT is not affected by Keyboard interrupts.
Bit[2] Mouse Enable
=1
=0
WDT is reset upon a Mouse interrupt
WDT is not affected by Mouse interrupts.
Bit[3] PWRLED Time-out enable
=1
Enables the Power LED to toggle at a 1Hz
rate with 50 percent duty cycle while the
Watch-dog Status bit is set.
=0
Disables the Power LED toggle during Watch-
dog timeout status.
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
.........
0011 = IRQ3
0010 = Invalid
0001 = IRQ1
0000 = Disable
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
WDT_CTRL
0xF4
C
=1
=0
WD timeout occurred
WD timer counting
Default = 0x00
Bit[1] Power LED Toggle Enable, R/W
Cleared by VTR
POR
=1
Toggle Power LED at 1Hz rate with 50 percent
duty cycle. (1/2 sec. on, 1/2 sec. off)
Disable Power LED Toggle
=0
Bit[2] Force Timeout, W
=1
Forces WD timeout event; this bit is self-clearing
Bit[3] P20 Force Timeout Enable, R/W
= 1
Allows rising edge of P20, from the Keyboard
Controller, to force the WD timeout event. A WD
timeout event may still be forced by setting the
Force Timeout Bit, bit 2.
= 0
P20 activity does not generate the WD timeout
event.
Note: The P20 signal will remain high for a minimum of
1us and can remain high indefinitely. Therefore, when P20
forced timeouts are enabled, a self-clearing edge-detect
circuit is used to generate a signal which is ORed with the
195
SMSC [ SMSC CORPORATION ]
