Environmental Monitoring and Control Device
Datasheet
10.2 SmBus Interface
tHD;STA
tLOW
tR
tF
SCLK
tSU;STA
tHD;STA
tHD;DAT
tSU;STO
tHIGH
tSU;DAT
SDA
tBUF
P
S
S
P
FIGURE 10.3 – SmBus TIMING
LIMITS
MIN
SYMBOL
FSMB
TSP
PARAMETER
SMB Operating Frequency
Spike Suppression
MAX
400
50
UNITS
kHz
ns
COMMENTS
Note 1
10
Note 2
TBUF
Bus free time between Stop and Start
1.3
0.6
µs
Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
µs
TSU:STA
TSU:STO
THD:DAT
TSU:DAT
TLOW
THIGH
TF
Repeated Start Condition setup time
Stop Condition setup time
Data hold time
Data setup time
Clock low period
0.6
0.6
0.3
100
1.3
µs
µs
µs
ns
µs
µs
ns
ns
pF
0.9
Note 3
Clock high period
0.6
20+0.1Cb
20+0.1Cb
Clock/Data Fall Time
Clock/Data Rise Time
Capacitive load for each bus line
300
300
400
TR
Cb
Note 1: The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified in the
System Management Bus Specification, Rev 1.1. This corresponds to the maximum clock frequency for
fast mode devices on the I2C bus. See “The I2C Bus Specification,” version 2.0, Dec. 1998.
Note 2: At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter.
Note 3: If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000
ns (TR max) + 250 ns (TSU:DAT min) @ 100 kHz) before the SCLK line is released.
SMSC EMC6D100/EMC6D101
Page 72
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
