Environmental Monitoring and Control Device
Datasheet
7.5.2 DETECTION OF A STALLED FAN
The fan failure bit in the interrupt status register is set in the event of a stalled fan. Note: the fan
tachometer reading register, which holds the count value, does not roll over - it stays at FFFFh in the event
of a stalled fan. The internal count register does rollover, however, and continuously counts to FFFFh as
long as the fan is stalled.
In the event the counter reaches FFFFh, the status bit is set and the count value is latched into the
register. The second subsequent fan tach pulse resets the counter but does not latch the count value.
Every second fan tach pulse latches the fan count value into the fan tachometer register except for this
special case.
The status bit for a fan failure is set when the tach reading is above the value set in the tach minimum
register. This interrupt status bit cannot be cleared by reading the status register as long as the count
value is above the minimum.
The tachometer can generate an INT# if properly enabled (EMC6D100 only).
7.5.3 FAN INTERRUPT STATUS BITS
The status bits for the fan events are in Interrupt Status Register 2 (42h). These bits are set when the
reading register is above the tachometer minimum. No interrupt status bits are set for fan events (even if
the fan is stalled) if the associated tachometer minimum is set to FFFFh (registers 54h-5Bh).
7.6
7.7
Linking Fan Tachometers to PWMs
The Fan Tach/PWM Interrupt select register is used to link the tachometers to the PWMs. This
association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status
registers. See the description of the PWM_TACH register. The default configuration is:
PWM1 -> TACH1.
PWM2 -> TACH2.
PWM3 -> TACH3 & TACH4.
System Synchronization
System Synchronization Pulses
Under normal operation, the PWM outputs will exhibit synchronization pulses in addition to the normal
PWM pulses. These pulses are 44us in duration, and repeat every 711us. These synchronization pulses
may be controlled by Register 83h: Synch Pulse Configuration Register: On/Off.
See section Chapter 8 Register Set for a description of this register.
See section Chapter 10 Timing Diagrams on page 71 for timing diagrams that illustrate PWM or
synchronization pulses, PWM’s with synchronization, and PWM’s without synchronization.
SMSC EMC6D100/EMC6D101
Page 36
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
