Environmental Monitoring and Control Device
Datasheet
To enable the INT# pin for the interrupt function, set bit 1 of the CONF register (7Fh) to ‘1’.
To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to ‘1’.
To enable temperature event, voltage events and/or fan events onto the INT# pin:
To enable out-of-limit temperature events set bit 5 of the Fan Temp Interrupt Enable register (80h) to
‘1’.
To enable out-of-limit voltage events set bit 3 of the Special Function Register (7Ch) to ‘1’
To enable Fan tachometer error events set bit 0 of the Fan Temp Interrupt Enable register (80h) to ‘1’.
See FIGURE 6.1 above. The following description assumes that the interrupt enable bits for all events are
set to enable the interrupt status bits to be set.
If the internal or remote temperature reading is not within the low or high temperature limits, INT# will be
active low (if the TEMP_EN bit is set). This pin will remain low while the Internal Temp Error bit or one or
both of the the Remote Temp Error bits in Interrupt Status 1 Register is set and the enable bit is set.
The INT# pin will not become active low as a result of the remote diode fault bits becoming set. However,
the occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause
the corresponding zone error bit to be set. This will cause the INT# pin to become active if enabled.
The INT# pin can be enabled to indicate out-of-limit voltages. Bit 3 of the Special Function register (7Ch)
is used to enable this option. When this bit is set, if one or more of the voltage readings is not within the
low or high limits, INT# will be active low. This pin will remain low while the associated voltage error bit in
the Interrupt Status Register 1, Interrupt Status Register 2 and Interrupt Status Register 3 is set.
The INT# pin can be enabled to indicate fan errors. Bit 0 of the Fan Temp Interrupt Enable register (80h) is
used to enable this option. This pin will remain low while the associated fan error bit in the Interrupt Status
Register 2 is set.
The INT# pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading the
interrupt status registers will cause the logic to attempt to clear the status bits; however, the status bits will
not clear if the interrupt stimulus is still active. The interrupt enable bit (Special Function Register bit[2])
should be cleared by software before reading the interrupt status registers to insure that the INT# pin will
be re-asserted while an interrupt event is active, when the INT_EN bit is written to ‘1’ again.
The INT# pin can also be deasserted by issuing an Alert Response Address Call. See the description in
the “SMBus Interface” section.
The INT# pin may only become active while the monitor block is operational.
6.6
Low Power Modes
The Hardware Monitor Block can be placed in a low-power mode by writing a ‘0’ to Bit[0] of the
Ready/Lock/Start Register (0x40). The low power mode that is entered is either sleep mode or shutdown
mode as selected using Bit[0] of the Special Function Register (7Ch). These modes do not reset any of the
registers of the Hardware Monitor Block. In both of these modes, the PWM pins are at 100% duty cycle.
6.6.1 SLEEP MODE
This is a low power mode in which bias currents are ‘on’ but the Hardware Monitor Block is not operating.
In this mode, the A/D converter and monitoring cycle will be turned off. Serial bus communication is still
possible with any register in the Hardware Monitor Block while in this low-power mode.
SMSC EMC6D100/EMC6D101
Page 25
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
