Chapter 8 Register Set
Definition for the Lock and Start columns:
Yes = Register is made read-only when the related bit is set; No = Register is not made read-only when the related bit is set.
Table 8.1 Register Summary
Reg
Addr
Read
/Write
Bit 7
MSb
Bit 0
LSb
Default
Value
Reg Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Lock
Start
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
R
Reserved
Vccp Reading
RES
7
RES
6
RES
5
RES
4
RES
3
RES
2
RES
RES
00h
N/A
N/A
00h
00h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
R
1
1
0
0
R
VCC Reading
7
6
5
4
3
2
No
R
Reserved
RES
RES
7
RES
RES
6
RES
RES
5
RES
RES
4
RES
RES
3
RES
RES
2
RES
RES
1
RES
RES
0
No
R
Reserved
No
R
Remote Diode 1 Temp Reading
Internal Temp Reading
Remote Diode 2 Temp Reading
Tach1 LSB
No
R
7
6
5
4
3
2
1
0
No
R
7
6
5
4
3
2
1
0
No
R
7
6
5
4
3
2
1
0
No
R
Tach1 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
No
R
R
Tach2 LSB
1
0
No
Tach2 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
No
R
Tach3 LSB
1
0
No
R
Tach3 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
No
R
Tach4 LSB
1
0
No
R
Tach4 MSB
15
7
14
6
13
5
12
4
11
3
10
2
9
8
No
R/W
Note 8.1
R/W
Note 8.1
R/W
Note 8.1
R
PWM1 Current Duty Cycle
1
0
Yes
Note 8.1
Yes
Note 8.1
Yes
Note 8.1
No
31h
32h
PWM2 Current Duty Cycle
PWM3 Current Duty Cycle
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
N/A
N/A
No
No
3Eh
3Fh
40h
Company ID
7
6
5
4
3
2
1
0
5Ch
6Ah
00h
No
No
No
R
Version / Stepping
Ready/Lock/Start
VER3
RES
VER2
RES
VER1
RES
VER0
RES
STP3
STP2
STP1
LOCK
STP0
START
No
R/W
Note 8.2
OVRID READY
Yes
Note 8.2
SMSC [ SMSC CORPORATION ]
