SMBus Fan Control with 1°C Accurate Temperature Monitoring
Datasheet
6.16
Fan Configuration Register
Table 6.18 Fan Configuration Register
ADDR.
R/W
REGISTER
B7
B6
FORCE
B5
PROG
B4
POLARITY
B3
B2
B1
B0
DEFAULT
CLK_
SEL
CLK_
OVR
4Ah
R/W
Fan Config
-
TACH_M[1:0]
20h
The Fan Configuration Register enables the Fan Control Look-Up Table and polarity of the PWM signal
driving the output.
Bit 6 - FORCE - enables the External Temperature Force Register. This bit is not used if the Fan
Control Look-Up Table is not used.
‘0’ (default) - the External Diode Force Register is not used. The measured External Diode
temperature is used to determine the position in the Fan Control Look-Up Table.
‘1’ - the External Temperature Force Register is used. When determining the position in the Fan
Control Look-Up Table, the contents of the External Temperature Force Register will be used
instead of the measured External Diode temperature. All limits will be checked against the
measured External Diode temperature as normal.
Bit 5 - PROG - enables the Fan Control Look-Up Table for update and sets fan driver output based
on Fan Control Look-Up Table values.
‘0’ - the Fan Setting Register and Fan Control Look-Up Table Registers are read-only and the Fan
Control Look-Up Table Registers will be used.
‘1’ (default) - the Fan Setting Register and Fan Control Look-Up Table Registers can be written.
The value written into the Fan Setting Register will be instantly applied to the fan driver and the
Fan Control Look-Up Table will not be used.
Bit 4 - POLARITY- sets the polarity of the Fan output driver. For the EMC2101-R, the value of this bit
is determined by the value of the pull-up resistor on the ALERT / TACH pin (see Table 5.1). When the
PWM default value is set at 100% duty cycle, the default value is set to ‘1’ and when the PWM default
value is set to 0% duty cycle, the default value is set to ‘0’. This occurs within 10ms after power-up.
‘0’ (default - EMC2101) - The polarity of the Fan output driver is non-inverted. A ‘00h’ setting will
correspond to a 0% duty cycle or minimum DAC output voltage.
‘1’ - The polarity of the Fan output driver is inverted. A ‘00h’ setting will correspond to a 100% duty
cycle or maximum DAC output voltage.
Bit 3 - CLK_SEL - Determines the base clock that is used to determine the final PWM frequency.
‘0’ (default) - The base clock that is used to determine the PWM frequency is 360kHz.
‘1’ - The base clock that is used to determine the PWM frequency is 1.4kHz.
Bit 2 - CLK_OVR - Overrides the CLK_SEL bit and uses the Frequency Divide Register to determine
the base PWM frequency. It is recommended that this bit be set for maximum PWM resolution.
‘0’ (default) - The base clock frequency for the PWM is determined by the CLK_SEL bit.
‘1’ (recommended) - The base clock that is used to determine the PWM frequency is set by the
Frequency Divide Register
Bit 1-0 - TACH_M[1:0] - Determines the basic operation of the tachometer input as shown in
Table 6.19.
Revision 2.53 (03-13-07)
SMSC EMC2101
DATA4S0HEET
SMSC [ SMSC CORPORATION ]
