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EMC1422_08 参数 Datasheet PDF下载

EMC1422_08图片预览
型号: EMC1422_08
PDF下载: 下载PDF文件 查看货源
内容描述: 1°C温度传感器与硬件热关断 [1∑C Temperature Sensor with Hardware Thermal Shutdown]
分类和应用: 传感器温度传感器
文件页数/大小: 38 页 / 579 K
品牌: SMSC [ SMSC CORPORATION ]
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1°C Temperature Sensor with Hardware Thermal Shutdown  
Datasheet  
Table 6.15 Consecutive Alert / THERM Settings  
NUMBER OF CONSECUTIVE OUT OF LIMIT  
2
1
0
MEASUREMENTS  
0
0
0
1
(default for CALRT[2:0])  
0
0
1
0
1
1
1
1
1
2
3
4
(default for CTHRM[2:0])  
APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When  
measuring 45nm Intel CPUs, the Ideality Setting should be 15h.  
6.14  
High Limit Status Register  
Table 6.16 High Limit Status Register  
ADDR.  
R/W  
REGISTER  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
DEFAULT  
High Limit  
Status  
35h  
R-C  
-
-
-
-
-
-
EHIGH  
IHIGH  
00h  
The High Limit Status Register contains the status bits that are set when a temperature channel high  
limit is exceeded. If any of these bits are set, then the HIGH status bit in the Status Register is set.  
Reading from the High Limit Status Register will clear all bits if. Reading from the register will also  
clear the HIGH status bit in the Status Register.  
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and  
any of these status bits are set.  
The status bits will remain set until read unless the ALERT pin is configured as a comparator output  
(see Section 5.3.2).  
Bit 1 - EHIGH - This bit is set when the External Diode channel exceeds its programmed high limit.  
Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.  
6.15  
Low Limit Status Register  
Table 6.17 Low Limit Status Register  
ADDR.  
R/W  
REGISTER  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
DEFAULT  
Low Limit  
Status  
36h  
R-C  
-
-
-
-
-
-
ELOW  
ILOW  
00h  
The Low Limit Status Register contains the status bits that are set when a temperature channel drops  
below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set.  
Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear  
the LOW status bit in the Status Register.  
The ALERT pin will be set if the programmed number of consecutive alert counts have been met and  
any of these status bits are set.  
SMSC EMC1422  
Revision 1.24 (02-05-08)  
DATA3S3HEET