1°C Temperature Sensor with Hardware Thermal Shutdown
Datasheet
6.11
Hardware Thermal Shutdown Limit Register
Table 6.12 Hardware Thermal Shutdown Limit Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Eh
R
Hardware Thermal
Shutdown Limit
128
64
32
16
8
4
2
1
N/A
This read only register returns the Hardware Thermal Shutdown Limit selected by the value of the pull-
up resistors on the ALERT and SYS_SHDN pins. The data represents the hardware set temperature
in °C using the active temperature setting set by the RANGE bit in the Configuration Register. See
Table 5.3 for the data format.
When the External Diode Temperature exceeds this limit, the SYS_SHDN pin is asserted and will
remain asserted until the External Diode Temperature drops below this limit minus 10°C.
6.12
Channel Mask Register
Table 6.13 Channel Mask Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
-
Channel
Mask
-
E
INT
MASK
1Fh
R/W
-
-
-
-
MASK
00h
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The
channel mask does not mask the SYS_SHDN pin.
Bit 1 - EMASK - Masks the ALERT pin from asserting when the External Diode channel is out of limit
or reports a diode fault.
‘0’ (default) - The External Diode channel will cause the ALERT pin to be asserted if it is out of
limit or reports a diode fault.
‘1’ - The External Diode channel will not cause the ALERT pin to be asserted if it is out of limit or
reports a diode fault.
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out
of limit.
‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.
‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.
6.13
Consecutive ALERT Register
Table 6.14 Consecutive ALERT Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
22h
R/W
Consecutive
ALERT
TIME
OUT
CTHRM[2:0]
CALRT[2:0]
-
70h
The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must
be detected in consecutive measurements before the ALERT or SYS_SHDN pin is asserted.
Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality.
SMSC EMC1422
Revision 1.24 (02-05-08)
DATA3S1HEET
SMSC [ SMSC CORPORATION ]
