Multiple Channel 1°C Temperature Sensor with Beta Compensation
Datasheet
‘1’ - The External Diode channel will not cause the ALERT pin to be asserted if it is out of limit or
reports a diode fault.
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out
of limit.
‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.
‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.
7.11
Consecutive ALERT Register
Table 7.12 Consecutive ALERT Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Consecutive
ALERT
TIME
OUT
22h
R/W
CTHRM[2:0]
CALRT[2:0]
-
70h
The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must
be detected in consecutive measurements before the ALERT or THERM pin is asserted. Additionally,
the Consecutive ALERT Register controls the SMBus Timeout functionality.
An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in
consecutive measurements will increment the consecutive alert counter. The counters will also be reset
if no out-of-limit condition or diode fault condition occurs in a consecutive reading.
When the ALERT pin is configured as an interrupt, when the consecutive alert counter reaches its
programmed value, the following will occur: the STATUS bit(s) for that channel and the last error
condition(s) (i.e. EHIGH) will be set to ‘1’, the ALERT pin will be asserted, the consecutive alert counter
will be cleared, and measurements will continue.
When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode
fault and low limit errors and only increment if the measured temperature exceeds the High Limit.
Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT pin will be
asserted, but the counter will not be reset. It will remain set until the temperature drops below the High
Limit minus the Therm Hysteresis value.
For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1412 device, the high
limits are set at 70°C, and none of the channels are masked, then the ALERT pin will be asserted after
the following four measurements:
1. Internal Diode reads 71°C and the external diode reads 69°C. Consecutive alert counter for INT is
incremented to 1.
2. Both the Internal Diode and the External Diode read 71°C. Consecutive alert counter for INT is
incremented to 2 and for EXT is set to 1.
3. The External Diode reads 71°C and the Internal Diode read 69°C. Consecutive alert counter for
INT is cleared and EXT is incremented to 2.
4. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for
INT is set to 1 and EXT is incremented to 3.
5. The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for
INT is incremented to 2 and EXT is incremented to 4. The appropriate status bits are set for EXT
and the ALERT pin is asserted. EXT counter is reset to 0 and all other counters hold the last value
until the next temperature measurement.
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.
‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely
without the device resetting its SMBus protocol.
Revision 1.41 (02-23-12)
SMSC EMC1412
DATA3S2HEET
SMSC [ SMSC CORPORATION ]
