Multiple Channel 1°C Temperature Sensor with Beta Compensation
Datasheet
The status bits (except E1THERM and ITHERM) will remain set until read unless the ALERT pin is
configured as a second THERM output (see Section 6.3.2).
Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either
the ALERT or THERM pins to be asserted.
Bit 6 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
When set, this bit will assert the ALERT pin.
Bit 5 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
When set, this bit will assert the ALERT pin.
Bit 4 - EHIGH - This bit is set when the External Diode channel exceeds its programmed high limit.
When set, this bit will assert the ALERT pin.
Bit 3 - ELOW - This bit is set when the External Diode channel drops below its programmed low limit.
When set, this bit will assert the ALERT pin.
Bit 2 - FAULT - This bit is asserted when a diode fault is detected. When set, this bit will assert the
ALERT pin.
Bit 1 - ETHERM - This bit is set when the External Diode channel exceeds the programmed Therm
Limit. When set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is
released at which point it will be automatically cleared.
Bit 0 - ITHERM - This bit is set when the Internal Diode channel exceeds the programmed Therm Limit.
When set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is released
at which point it will be automatically cleared.
7.4
Configuration Register
Table 7.4 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
03h
09h
MASK_
ALL
RUN/
STOP
ALERT/
COMP
DAVG_
DIS
R/W
Configuration
RECD
-
RANGE
-
00h
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
‘0’ - (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT
pin will be asserted.
‘1’ - - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is
configured in comparator mode. The Status Register will be updated normally.
Bit 6 - RUN / STOP - Controls Active/Standby modes.
‘0’ (default) - The device is in Active mode and converting on all channels.
‘1’ - The device is in Standby mode and not converting.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.
‘0’ (default) - The ALERT pin acts as described in Section 6.3.
‘1’ - The ALERT pin acts in comparator mode as described in Section 6.3.2. In this mode the
MASK_ALL bit is ignored.
Bit 4 - RECD - Disables the Resistance Error Correction (REC) for the External Diode.
‘0’ (default) - REC is enabled for the External Diode.
‘1’ - REC is disabled for the External Diode.
Revision 1.41 (02-23-12)
SMSC EMC1412
DATA2S8HEET
SMSC [ SMSC CORPORATION ]
