Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications
Datasheet
6.3
Status Register 02h
Table 6.3 Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
02h
R-C
Status
BUSY
IHIGH
ILOW
EHIGH ELOW
FAULT
ETHERM ITHERM
00h
The Status Register reports the operating status of the Internal Diode and External Diode channels.
When any of the bits are set (excluding the BUSY bit) either the ALERT / THERM2 or THERM pin is
being asserted.
The ALERT / THERM2 and THERM pins are controlled by the respective consecutive alert counters
(see Section 6.11) and will not be asserted until the programmed consecutive alert count has been
reached. The status bits (except ETHERM and ITHERM) will remain set until read unless the ALERT
pin is configured as a second THERM output (see Section 5.4).
Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either
the ALERT / THERM2 or THERM pin to be asserted.
Bit 6 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit.
When set, this bit will assert the ALERT / THERM2 pin.
Bit 5 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
When set, this bit will assert the ALERT / THERM2 pin.
Bit 4 - EHIGH - This bit is set when the External Diode channel exceeds its programmed high limit.
When set, this bit will assert the ALERT / THERM2 pin.
Bit 3 - ELOW - This bit is set when the External Diode channel drops below its programmed low limit.
When set, this bit will assert the ALERT / THERM2 pin.
Bit 2 - FAULT - This bit is asserted when a diode fault is detected. When set, this bit will assert the
ALERT / THERM2 pin.
Bit 1 - ETHERM - This bit is set when the External Diode channel exceeds the programmed Therm
Limit. When set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is
released at which point it will be automatically cleared.
Bit 0 - ITHERM - This bit is set when the Internal Diode channel exceeds the programmed Therm Limit.
When set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is released
at which point it will be automatically cleared.
6.4
Configuration Register 03h / 09h
Table 6.4 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
03h
09h
MASK_
ALL
RUN/
STOP
DAVG_
DIS
R/W
Configuration
ALERT/
THERM2
RECD
-
RANGE
-
00h
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Revision 1.0 (07-11-13)
28
SMSC EMC1182
DATASHEET
SMSC [ SMSC CORPORATION ]
