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EMC1047-1-AIZL-TR 参数 Datasheet PDF下载

EMC1047-1-AIZL-TR图片预览
型号: EMC1047-1-AIZL-TR
PDF下载: 下载PDF文件 查看货源
内容描述: [Serial Switch/Digital Sensor, 11 Bit(s), 2Cel, Square, Surface Mount, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, TSSOP-10]
分类和应用: 输出元件传感器换能器
文件页数/大小: 37 页 / 264 K
品牌: SMSC [ SMSC CORPORATION ]
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1°C Multiple Temperature Sensor with Beta Compensation and Hottest of Thermal Zones  
Datasheet  
2. Both the Internal Diode and the External Diode 1 read 71°C and External Diode 2 reads 68°C.  
Consecutive alert counter for INT is incremented to 2 and for EXT1 is set to 1.  
3. The External Diode 1 reads 71°C and both the Internal Diode and External Diode 2 read 69°C.  
Consecutive alert counter for INT and EXT2 are cleared and EXT1 is incremented to 2.  
4. The Internal Diode reads 71°C and both external diodes read 71°C. Consecutive alert counter for  
INT is set to 1, EXT2 is set to 1, and EXT1 is incremented to 3.  
5. The Internal Diode reads 71°C and both the external diodes read 71°C. Consecutive alert counter  
for INT is incremented to 2, EXT2 is set to 2, and EXT1 is incremented to 4. The HIGH status bit  
are set for EXT1. The EXT1 counter is reset to 0 and all other counters hold the last value until  
the next temperature measurement.  
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.  
„
„
‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely  
without the device resetting its SMBus protocol.  
‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms,  
then the device will reset the SMBus protocol.  
Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of  
limit condition or diode fault before the STATUS bits is asserted. All temperature channels use this  
value to set the respective counters. The bits are decoded as shown in Table 5.13. The default setting  
is 1 consecutive out of limit conversion.  
APPLICATION NOTE: If one of the fault queues is not cleared and the CALRT[2:0] bits are updated, the update  
won’t take affect until fault queue is cleared. All the fault queues are independent so those  
that are empty will be updated immediately.  
Table 5.13 Consecutive Alert Settings  
NUMBER OF CONSECUTIVE OUT OF LIMIT  
2
1
0
MEASUREMENTS  
0
0
0
1
0
0
1
1
1
1 (default for CALRT[2:0])  
0
2
1
1
3
4
All Others  
1 (CALRT[2:0]),  
5.10 Beta Configuration Register  
Table 5.14 Beta Configuration Register  
ADDR.  
R/W  
REGISTER  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
DEFAULT  
25h  
R/W  
External Diode 1  
Beta Configuration  
-
-
-
-
AUTO1  
BETA1[2:0]  
08h  
26h  
71h  
R/W  
R/W  
External Diode 2  
Beta Configuration  
-
-
-
-
-
-
-
-
AUTO2  
AUTO4  
BETA2[2:0]  
BETA4[2:0]  
08h  
08h  
External Diode 4  
Beta Configuration  
SMSC EMC1046/EMC1047  
Revision 0.69 (06-29-09)  
DATA2S9HEET