BIT
DESCRIPTION
7
- This signals the processor that a completed character is present in
RX BUFFER FULL
the Receive Buffer Register for transfer to the processor. This bit is set when a character
has been loaded from the receive deserialization logic to the Receive Buffer Register.
This bit is cleared by:
A)
B)
C)
Reading the Receive Buffer Register
Asserting the RECEIVER RESET bit in the Control Register
Asserting internal reset
Table 5 – COM81C17 CONTROL REGISTER DESCRIPTION (BITS 0-7)
DESCRIPTION
BIT
0
Not used (test mode bit, must be zero).
1
– This bit controls the nCP2 output pin. Data at the output is the logical
CP2
compliment of the register data. When the CP2 bit is set, the nCP2 pin is forced low.
When CP2 is RTS, a 1 to 0 transition of the CP2 bit will cause the nCP2 pin to go high
one TXc time after the last serial bit has been transmitted.
2
– This bit when reset will disable the setting of the RX BUFFER FULL bit
RX ENABLE
in the Status Register which informs the processor of the availability of a received
character in the Receive Buffer Register. The error bits in the Status Register will be
cleared and will remain cleared when RX is disabled.
3
4
5
– This will reset the receiver block only.
– This will reset the transmitter block only.
RX RESET
TX RESET
TX ENABLE
– Data transmission cannot take place by the TPUART unless this bit is
set. When this bit is reset (disable), transmission will be disabled only after the
previously written data has been transmitted.
6
7
– This bit when set will reset the parity, overrun, and framing error
bits in the Status Register. No latch is provided in the Control Register for saving this
bit; therefore there is no need to clear it (error reset = d6.RS.nWR).
RESET ERRORS
– This bit enables the resetting of the internal circuitry and initializes
INTERNAL RESET
access to address 0 to be sequential.
10
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