OVERVIEW
The COM20051I is essentially a network board-in-a-chip. It takes an 80C32 microcontroller core and an ARCNET
controller and integrates them into a single device. ARCNET is a token passing-based protocol that combines
powerful flow control, error detection, and diagnostic capabilities to deliver fast and reliable messages. The
COM20051I supports a variety of data rates (5 Mbps to 156 Kbps), topologies (bus, star, tree), and media types (RS-
485, coax, twisted pair, fiber optic, and powerline) to suit any type of application.
The ARCNET network core of the COM20051I contains many features that make network development simple and
easy to comprehend. Diagnostic features, such as Receive All, Duplicate ID Detection, Reconfiguration Detection,
Token, and Receiver Detection, all combine to make the COM20051I simple to use and to implement in any
environment. The ARCNET protocol itself is relatively simple to understand and very flexible. A wide variety of
support products are available to assist in network development, such as software drivers, line drivers, boards, and
development kits. The COM20051I implements a full-featured 16MHz, Intel-compatible 80C32 microcontroller with all
of the standard peripheral functions, including a full duplex serial port, two timer/counters, one 8-bit general purpose
digital I/O port, and interrupt controller. The 8051 architecture has long been a standard in the embedded control
industry for low-level data acquisition and control. ARCNET and the 8051 form a simple solution for many of today's
and tomorrow's low-level networking solutions.
In addition to the 80C32 and the ARCNET network core, the COM20051I contains all the address decoding and
interrupt routing logic to interface the network core to the 80C32 core. The integrated 8051/ARCNET combination
provides an extremely cost-effective and space-efficient solution for industrial networking applications. The
COM20051I can be used in a stand-alone embedded application, executing control algorithms or performing data
acquisition and communicating data in a master/slave or
peer-to-peer
configuration, or used as a slave processor
handling communication tasks in a multi-processing system.
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2-9
10
11
12
NAME
Receive In
P1.0-1.7
Reset
P3.0
nPulse 1
SYMBOL
RXIN
P1.0-1.7
RESET
P3.0
nPULSE1
DESCRIPTION
Input. Network receiver input.
Input/Output. Port 1 of the 8051. General purpose
digital I/O port.
Input. Active high reset.
Input/Output. Port 3 bit 0 of the 8051. RX input of
serial port.
Output. Network output. Open-drain when
backplane mode is invoked, otherwise it is a push-
pull output.
Input/Output. Port 3 bits 1-7 of the 8051.
Input. Oscillator inputs 1 and 2.
Ground pin.
Output. Network output. Outputs a synchronous
clock at 2x the data rate when backplane mode is
invoked.
Input/Output. Port 2 of the 8051. High order address
bus.
Output.
Output.
Output. This signal is used to enable the drivers for
transmitting. The polarity of this signal is
programmable by grounding the nPULSE2 pin prior
to the POWER-UP.
nPULSE2 floating prior to the power-up = TXEN
active high
nPULSE2 grounded prior to the power-up = TXEN
active low. (This option is available only in the
Backplane mode).
13-19
20, 21
22
23
P3.1-3.7
P3.1-3.7
Crystal Oscillator XTAL1,
XTAL2
Ground
nPulse 2
VSS
nPULSE2
24-31
32
33
34
P2.0-2.7
P2.0-2.7
nProgram Store nPSEN
Enable
Address Latch
Enable
ALE
Transmit Enable TXEN
SMSC DS – COM20051I
Page 5
Rev. 03/27/2000
SMSC [ SMSC CORPORATION ]
