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COM20022I-3.3V 参数 Datasheet PDF下载

COM20022I-3.3V图片预览
型号: COM20022I-3.3V
PDF下载: 下载PDF文件 查看货源
内容描述: 10 Mbps的ARCNET ( ANSI 878.1 )控制器2Kx8片上RAM [10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM]
分类和应用: 控制器
文件页数/大小: 73 页 / 465 K
品牌: SMSC [ SMSC CORPORATION ]
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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
TABLE OF CONTENTS
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
4.2
4.3
4.4
4.5
4.2.1
General Description ............................................................................................................. 6
Pin Configuration................................................................................................................. 7
Description of Pin Functions ............................................................................................... 8
Protocol Description........................................................................................................... 11
Selecting Clock Frequencies Above 2.5 Mbps .......................................................................................11
Network Protocol ............................................................................................................................... 11
Data Rates......................................................................................................................................... 11
Network Reconfiguration ................................................................................................................... 12
Broadcast Messages......................................................................................................................... 13
Extended Timeout Function .............................................................................................................. 13
4.5.1
4.5.2
4.5.3
Response Time.......................................................................................................................................13
Idle Time.................................................................................................................................................13
Reconfiguration Time..............................................................................................................................13
Invitations To Transmit ...........................................................................................................................14
Free Buffer Enquiries..............................................................................................................................14
Data Packets ..........................................................................................................................................14
Acknowledgements.................................................................................................................................15
Negative Acknowledgements .................................................................................................................15
4.6
Line Protocol ..................................................................................................................................... 13
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
Chapter 5
5.1
5.2
5.1.1
5.1.2
5.2.1
5.2.2
5.2.3
5.2.4
System Description............................................................................................................. 16
Selection of 8/16-Bit Access ...................................................................................................................19
High Speed CPU Bus Timing Support ....................................................................................................19
Traditional Hybrid Interface.....................................................................................................................21
Backplane Configuration.........................................................................................................................21
Differential Driver Configuration..............................................................................................................23
Programmable TXEN Polarity.................................................................................................................23
Microcontroller Interface.................................................................................................................... 16
Transmission Media Interface ........................................................................................................... 21
Chapter 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
6.2.12
6.2.13
6.2.14
Functional Description....................................................................................................... 25
Interrupt Mask Register (IMR) ................................................................................................................27
Data Register..........................................................................................................................................27
Tentative ID Register ..............................................................................................................................27
Node ID Register ....................................................................................................................................28
Next ID Register .....................................................................................................................................28
Status Register .......................................................................................................................................28
Diagnostic Status Register .....................................................................................................................28
Command Register.................................................................................................................................28
Address Pointer Registers ......................................................................................................................29
Configuration Register ........................................................................................................................29
Sub-Address Register .........................................................................................................................29
Setup 1 Register .................................................................................................................................29
Setup 2 Register .................................................................................................................................29
Bus Control Register ...........................................................................................................................30
Sequential Access Memory ....................................................................................................................39
Access Speed.........................................................................................................................................40
Software Interface...................................................................................................................................40
Selecting RAM Page Size.......................................................................................................................40
Transmit Sequence.................................................................................................................................42
Receive Sequence..................................................................................................................................43
Microsequencer................................................................................................................................. 25
Internal Registers .............................................................................................................................. 27
6.3
Internal RAM...................................................................................................................................... 39
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.4
Command Chaining........................................................................................................................... 44
Page 3
Revision 03-08-07
SMSC COM20022I 3.3V Rev.C
DATASHEET