10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Table 8.1 - DMA Timing
PARAMETER
MIN
TYP
MAX
30
UNIT
NOTE
t1
t2
nDACK Inactive Pulse Width
ns
(Note 8.1)
The First DREQ Assertion Delay After Writing Low
Pointer
4 Tarb
5
Tarb
5Tarb
+40ns
40
(Note 8.3)
(Note 8.4)
(Note 8.2)
t3
t4
t5
DREQ Assert Delay from nREFEX Active at
Programmable Burst Transfer Mode
0
0
ns
ns
DREQ Assertion Delay from Write/Read Inactive at
Non-Burst Transfer Mode
40
GTTM
bit =0
7Txtl
15Txtl
8Txtl
+40ns
16Txtl
+40ns
DREQ Assertion Delay from nDACK
Inactive due to Timeout of Gate Timer at
Programmable Burst Transfer Mode
GTTM
bit=1
(Note 8.4)
(Note 8.4)
t6
t7
DREQ Negation Delay from Write/Read Active
0
0
40
40
ns
ns
DREQ Negation Delay from TC and Write/Read
Active
(Note 8.4)
(Note 8.4)
t8
t9
Data Access Time from Read Active
Data Float Delay from Read Inactive
40
20
ns
ns
ns
ns
0
t10 nREFEX Active Pulse Width
t11 Write Active Pulse Width
20
20
(Note 8.4,
Note 8.5)
CASE
1W
CASE
2W
65
60
ns
ns
ns
ns
(Note 8.4,
Note 8.5)
t12 Read Active Pulse Width
CASE
1R
CASE
2R
100
20
(Note 8.4)
t13 Active Pulse Overlap Width between TC and
Write/Read
(Note 8.4,
Note 8.5)
t14 Write/Read Inactive Pulse Width
CASE1w/1R
20
30
ns
ns
CASE2w/2R
(Note 8.1,
Note 8.4)
t15 Write Cycle Interval Period
t16 Read Cycle Interval Period
4Tarb
(Note 8.1,
Note 8.4,
Note 8.5)
CASE1R
CASE2R
4Tarb
4Tarb+3
0nS
(Note 8.4)
(Note 8.4)
t17 Data Setup to Write Inactive
30
10
20
20
20
10
10
30
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
t18 Data Hold From Write Inactive
t19 nCS High Setup to nDACK Active
t20 nCS High Hold from nDACK Inactive
t21 DREQ Active Setup to nDACK Active
t22 DIR Setup to nDS Low (Motorola mode only)
t23 DIR Hold from nDS High (Motorola mode only)
t24 nDACK Setup to Write/Read Active
t25 nDACK Hold After Write/Read Inactive
t26 nREFEX Inactive Time
(Note 8.4)
(Note 8.4)
(Note 8.2)
3Txtl
SMSC COM20022I 3V
Page 77
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
