10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Note 8.1 Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit.
SLOWARB must set to “1” if the data rate is over 5 Mbps. (i.e. 10 Mbps)
Tarb is Topr at SLOWARB=0 and Tarb is 2Topr at SLOWARB=1.
Topr is the period of Operation Clock Frequency. It depends on the CKUP1 and CKUP0 bits.
Note 8.2 Txtl is a period of external XTAL oscillation frequency.
Note 8.3 The nREFEX pin must not be Low while nDACK is Low.
Note 8.4 “Write” means write signal and “Read” means read signal. “Write/Read” means write or read signal.
At INTEL MODE, write signal is nWR and read signal is nRD.
At MOTOROLA MODE, write signal is nDS when DIR is Low and the read signal is nDS when DIR is High.
Note 8.5 Conditions of CASE1W, CASE2W, CASE1R and CASE2R are shown below;
CASE1W : BUSTMG pin = High
CASE2W : BUSTMG pin = Low
CASE1R : BUSTMG pin = High and RBUSTMG bit = 0
CASE2R : BUSTMG pin = Low or RBUSTMG bit = 1
Revision 02-27-06
Page 78
SMSC COM20022I 3V
DATASHEET
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