10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
this point. Once the "Enable Receive to Page fnn" command is issued, the microcontroller attends to other
duties.
There is no way of knowing how long the new reception will take, since another node may transmit a
packet at any time. When another node does transmit a packet to this node, and if the "Define
Configuration" command has enabled the reception of long packets, the COM20022I 3V interprets the
packet as either a long or short packet, depending on whether the content of the buffer location 2 is zero or
non-zero. The format of the buffer is shown in Figure 5.7. Address 0 contains the Source Identifier (SID),
Address 1 contains the Destination Identifier (DID), and Address 2 contains, for short packets, the value
256-N, where N represents the message length, or for long packets, the value 0, indicating that it is indeed
a long packet. In the latter case, Address 3 contains the value 512-N, where N represents the message
length. Note that on reception, the COM20022I 3V deposits packets into the RAM buffer in the same
format that the transmitting node arranges them, which allows for a message to be received and then
retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the
packet is received and stored correctly in the selected buffer, the COM20022I 3V sets the RI bit to logic "1"
to signal the microcontroller that the reception is complete.
MSB
TRI
LSB
RI
TA
POR
TEST
RECON
TMA
TMA
TTA
TRI
TTA
Figure 6.4 - Command Chaining Status Register Queue
6.4
Command Chaining
The Command Chaining operation allows consecutive transmissions and receptions to occur without host
microcontroller intervention.
Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status
bits, are pipelined.
In order for the COM20022I 3V to be compatible with previous SMSC ARCNET device drivers, the device
defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the
Command Chaining Mode must be enabled via a logic "1" on bit 6 of the Configuration Register.
In Command Chaining, the Status Register appears as in Figure 6.4.
The following is a list of Command Chaining guidelines for the software programmer. Further detail can be
found in the Transmit Command Chaining and Receive Command Chaining sections.
The device is designed such that the interrupt service routine latency does not affect performance.
Up to two outstanding transmissions and two outstanding receptions can be pending at any given
time. The commands may be given in any order.
Up to two outstanding transmit interrupts and two outstanding receive interrupts are stored by the
device, along with their respective status bits.
The Interrupt Mask bits act on TTA (Rising Transition on Transmitter Available) for transmit operations
and TRI (Rising Transition of Receiver Inhibited) for receive operations. TTA is set upon completion
of a packet transmission only. TRI is set upon completion of a packet reception only. Typically there is
no need to mask the TTA and TRI bits after clearing the interrupt.
SMSC COM20022I 3V
Page 51
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
