10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
PIN NO
NAME
SYMBOL
I/O
DESCRIPTION
38
Terminal
Count
TC
IN
Terminal Count signal. Active polarity is
programmable. Default is active high. When
BUSTMG is High, this signal is connected to the
internal pull-up resistor.
40
Refresh
Execution
nREFEX
IN
Refresh execution signal. Falling edge detection.
This signal is connected to the internal pull-up
resistor.
TRANSMISSION MEDIA INTERFACE
24
25
nPulse 1
nPulse 2
nPULSE1
OUT
In Normal Mode, these active low signals carry the
transmit data information, encoded in pulse format as
DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull or
open-drain), while the nPULSE2 signal provides a
clock with frequency of doubled data rate. nPULSE1
is connected to a weak internal pull-up resistor on
the open/drain driver in backplane mode.
nPULSE2
I/O
28
29
Receive In
RXIN
IN
This signal carries the receive data information from
the line transceiver.
nTransmit
Enable
nTXEN
OUT
Transmission Enable signal. Active polarity is
programmable through the nPULSE2 pin.
nPULSE2 floating before power-up;
nTXEN active low
nPULSE2 grounded before power-up;
nTXEN active high (this option is only available in
Back Plane mode)
21
22
Crystal
Oscillator
XTAL1
XTAL2
IN
An external crystal should be connected to these
pins. Oscillation frequency range is from 10 MHz to
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 with a 390ohm pull-up
resistor, and XTAL2 should be left floating.
OUT
8,20,
32,43
6,11,
Power
Supply
VDD
VSS
PWR +5 Volt power supply pins.
Ground
PWR Ground pins.
18,23,
30,41
19,27
N/C
N/C
Non-connection
SMSC COM20022I 3V
Page 9
Revision 02-27-06
DATASHEET