10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Figure 8.9 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle.................................................................68
Figure 8.10 - Non-Multiplexed Bus, 80XX-Like Control Signals; Write Cycle...............................................................69
Figure 8.11 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle...............................................................70
Figure 8.12 - Non-Multiplexed Bus, 68XX-Like Control Signals; Write Cycle...............................................................71
Figure 8.13 - Normal Mode Transmit or Receive Timing..............................................................................................72
Figure 8.14 - Backplane Mode Transmit or Receive Timing ........................................................................................73
Figure 8.15 - TTL Input Timing on XTAL1 Pin..............................................................................................................74
Figure 8.16 - Reset and Interrupt Timing .....................................................................................................................74
Figure 8.17 - DMA Timing (Intel Mode 80XX) ..............................................................................................................75
Figure 8.18 - DMA Timing (Motorola Mode 68XX) .......................................................................................................76
Figure 8.19 - 48 Pin TQFP Package Outline................................................................................................................79
Figure 9.1 - Effect of the EF Bit on the TA/RI Bit..........................................................................................................82
Figure 10.1 - Example of Interface of Circuit Diagram to ISA Bus................................................................................83
LIST OF TABLES
Table 5.1 - Typical Media .............................................................................................................................................29
Table 6.1 - Read Register Summary............................................................................................................................30
Table 6.2 - Data Register at 16 Bit Access ..................................................................................................................31
Table 6.3 - Write Register Summary............................................................................................................................31
Table 6.4 - Data Register at 16 Bit Address.................................................................................................................32
Table 6.5 - Status Register ...........................................................................................................................................36
Table 6.6 - Diagnostic Status Register..........................................................................................................................37
Table 6.7 - Command Register.....................................................................................................................................38
Table 6.8 - Address Pointer High Register....................................................................................................................39
Table 6.9 - Address Pointer Low Register.....................................................................................................................39
Table 6.10 - Sub Address Register...............................................................................................................................40
Table 6.11 - Configuration Register ..............................................................................................................................40
Table 6.12 - Setup 1 Register.......................................................................................................................................42
Table 6.13 - Setup 2 Register.......................................................................................................................................43
Table 6.14 - Bus Control Register.................................................................................................................................44
Table 6.15 - DMA Count Register.................................................................................................................................45
Table 8.1 - DMA Timing................................................................................................................................................77
Table 8.2 - 48 Pin TQFP Package Parameters............................................................................................................79
SMSC COM20022I 3V
Page 5
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
