10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 8.1 - DMA Timing
UNIT
PARAMETER
MIN
TYP
MAX
30
NOTE
t1
t2
nDACK Inactive Pulse Width
ns
The First DREQ Assertion Delay After Writing Low
Pointer
4 Tarb
5
5Tarb
+40ns
40
Note 1
Tarb
t3
t4
t5
DREQ Assert Delay from nREFEX Active at
Programmable Burst Transfer Mode
0
0
ns
ns
Note 3
Note 4
Note 2
DREQ Assertion Delay from Write/Read Inactive at Non-
Burst Transfer Mode
40
GTTM
bit =0
7Txtl
15Txtl
8Txtl
+40ns
16Txtl
+40ns
DREQ Assertion Delay from nDACK
Inactive due to Timeout of Gate Timer
at Programmable Burst Transfer Mode
GTTM bit=1
t6
t7
DREQ Negation Delay from Write/Read Active
DREQ Negation Delay from TC and Write/Read Active
Data Access Time from Read Active
0
0
40
40
40
20
ns
ns
ns
ns
ns
ns
Note 4
Note 4
Note 4
Note 4
t8
t9
Data Float Delay from Read Inactive
0
t10
t11
nREFEX Active Pulse Width
20
20
Write Active Pulse Width
CASE 1W
Note
4,5
CASE 2W
CASE 1R
65
60
ns
ns
t12
Read Active Pulse Width
Note
4,5
CASE 2R
100
20
ns
ns
ns
ns
t13
t14
Active Pulse Overlap Width between TC and Write/Read
Note 4
Write/Read Inactive Pulse Width
CASE1w/1R
CASE2w/2R
20
Note
4,5
30
t15
t16
Write Cycle Interval Period
Read Cycle Interval Period
4Tarb
Note
1,4
CASE1R
CASE2R
4Tarb
Note
1,4,5
4Tarb+3
0nS
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
Data Setup to Write Inactive
30
10
20
20
20
10
10
30
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 4
Note 4
Data Hold From Write Inactive
nCS High Setup to nDACK Active
nCS High Hold from nDACK Inactive
DREQ Active Setup to nDACK Active
DIR Setup to nDS Low (Motorola mode only)
DIR Hold from nDS High (Motorola mode only)
nDACK Setup to Write/Read Active
nDACK Hold After Write/Read Inactive
nREFEX Inactive Time
Note 4
Note 4
Note 2
3Txtl
Notes:
1. Tarb is the ARBITRATION CLOCK PERIOD. It depends on Topr and SLOWARB bit.
SLOWARB must set to “1” if the data rate is over 5 Mbps. (i.e. 10 Mbps)
Tarb is Topr at SLOWARB=0 and Tarb is 2Topr at SLOWARB=1.
Topr is the period of Operation Clock Frequency. It depends on the CKUP1 and CKUP0 bits.
2. Txtl is a period of external XTAL oscillation frequency.
3. The nREFEX pin must not be Low while nDACK is Low.
Revision 09-27-07
Page 76
SMSC COM20022I
DATASHEET
SMSC [ SMSC CORPORATION ]
