10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
Datasheet
Table 6.7 - Address Pointer Low Register
SYMBOL DESCRIPTION
A7-A0
BIT
BIT NAME
Address 7-0
7-0
These bits hold the lower 8 address bits which provide the
addresses to RAM.
When 16 bit access is enabled, (W16=1), A0 becomes the SWAP
bit. Swap bit is undefined after a hardware reset. The swap bit
must be set before W16 bit is set to “1”. The swap bit is used to
swap the upper and lower data byte. The swap bit influences
both CPU cycle and DMA cycle. See Table Below.
SWAP
Detected Host Interface
Mode
Swap Bit
D15-D8
Pin
D7-D0 Pin
Intel 80xx Mode
(RD, WR Mode)
Motorola 68xx Mode
(DIR, DS Mode)
0
1
0
1
Odd
Even
Even
Odd
Even
Odd
Odd
Even
Table 6.8 - Sub Address Register
BIT
BIT NAME
Reserved
SYMBOL
DESCRIPTION
7-3
These bits are undefined.
2,1,0 Sub Address 2,1,0
SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2
SUBAD1
SUBAD0
Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Tentative ID \ (Same
Node ID
\ as in
Setup 1
Next ID
/ Config
/ Register)
Setup 2
Bus Control
DMA Count
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by writing
the Configuration Register.
SMSC COM20022I
Page 41
Revision 09-27-07
DATASHEET
SMSC [ SMSC CORPORATION ]
