5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Table 7 - Address Pointer High Register
SYMBOL DESCRIPTION
BIT
BIT NAME
Read Data
7
RDDATA
This bit tells the COM20020I whether the following access
will be a read or write. A logic "1" prepares the device for a
read, a logic "0" prepares it for a write.
6
Auto Increment
AUTOINC
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic
increment of the pointer after each access, while a logic "0"
disables this function. Please refer to the Sequential
Access Memory section for further detail.
5-3 (Reserved)
These bits are undefined.
2-0 Address 10-8
A10-A8
These bits hold the upper three address bits which provide
addresses to RAM.
Table 8 - Address Pointer Low Register
SYMBOL DESCRIPTION
A7-A0
BIT
BIT NAME
7-0 Address 7-0
These bits hold the lower 8 address bits which provide the
addresses to RAM.
Table 9 - Sub Address Register
BIT
BIT NAME
SYMBOL
DESCRIPTION
7-3 Reserved
These bits are undefined.
2,1,0 Sub Address 2,1,0 SUBAD
2,1,0
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0
Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0Tentative ID \ (Same
1Node ID
0Setup 1
1Next ID
\ as in
/ Config
/ Register)
0Setup 2
1Reserved
0Reserved
1Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by
writing the Configuration Register.
Table 10 - Configuration Register
SYMBOL DESCRIPTION
RESET
BIT
BIT NAME
Reset
7
A software reset of the COM20020I is executed by writing a
logic "1" to this bit. A software reset does not reset the
microcontroller interface mode, nor does it affect the
Configuration Register. The only registers that the software
reset affect are the Status Register, the Next ID Register, and
the Diagnostic Status Register. This bit must be brought
back to logic "0" to release the reset.
SMSC COM20020I 3.3V
Page 31
Revision 12-06-06
DATASHEET