5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TABLE OF CONTENTS
2.0
3.0
4.0
5.0
GENERAL DESCRIPTION..............................................................................................................................5
PIN CONFIGURATIONS .................................................................................................................................6
DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8
PROTOCOL DESCRIPTION.........................................................................................................................11
5.1
5.2
5.3
5.4
5.5
5.6
NETWORK PROTOCOL ..................................................................................................................................11
DATA RATES ...............................................................................................................................................11
NETWORK RECONFIGURATION.......................................................................................................................12
BROADCAST MESSAGES ...............................................................................................................................12
EXTENDED TIMEOUT FUNCTION.....................................................................................................................12
LINE PROTOCOL ..........................................................................................................................................13
6.0
SYSTEM DESCRIPTION...............................................................................................................................15
6.1
6.2
MICROCONTROLLER INTERFACE ....................................................................................................................15
TRANSMISSION MEDIA INTERFACE .................................................................................................................19
7.0
FUNCTIONAL DESCRIPTION......................................................................................................................24
7.1
7.2
7.3
7.4
7.5
7.6
MICROSEQUENCER ......................................................................................................................................24
INTERNAL REGISTERS...........................................................................................................................25
INTERNAL RAM ............................................................................................................................................35
COMMAND CHAINING....................................................................................................................................40
INITIALIZATION SEQUENCE ............................................................................................................................42
IMPROVED DIAGNOSTICS ..............................................................................................................................42
8.0
OPERATIONAL DESCRIPTION ...................................................................................................................45
8.1
8.2
MAXIMUM GUARANTEED RATINGS*................................................................................................................45
DC ELECTRICAL CHARACTERISTICS ...............................................................................................................45
9.0
TIMING DIAGRAMS......................................................................................................................................48
PACKAGE OUTLINES..................................................................................................................................60
APPENDIX A.................................................................................................................................................62
10.0
11.0
12.0
APPENDIX B.................................................................................................................................................65
12.1
SOFTWARE IDENTIFICATION OF THE COM20020I REV B, REV C AND REV D.....................................................65
LIST OF FIGURES
Figure 1 - COM20020I OPERATION ...........................................................................................................................10
Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE...............................................16
Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE......................................17
Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18
Figure 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS................................................20
Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0.............................................................................................20
Figure 7 - INTERNAL BLOCK DIAGRAM ....................................................................................................................22
Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35
Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38
Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE...............................................................................40
Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................48
Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................49
Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50
SMSC COM20020I 3.3V
Page 3
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
