5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP
PIN NO
44, 45,
46
NAME
Address
0-2
SYMBOL
I/O
DESCRIPTION
MICROCONTROLLER INTERFACE
A0/nMUX
IN
On a non-multiplexed mode, A0-A2 are address
input bits. (A0 is the LSB) On a multiplexed
A1
IN
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A2/ALE
IN
A1 is connected to an internal pull-up resistor.
I/O
AD0-AD2,
On a non-multiplexed bus, these signals are used as
D3-D7
the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines. D3-D7
are always used for data only. These signals are
connected to internal pull-up resistors.
N/C
I/O
Non-connection
1, 2, 4,
7, 9, 10,
12, 13
Data 0-7
47, 48,
3, 5,
14-17
37
N/C
nWrite/
Direction
nWR/DIR
IN
39
nRead/
nData
Strobe
nReset In
nInterrupt
nChip
Select
N/C
Read/Write
Bus Timing
Select
nRD/nDS
IN
31
34
36
42
26
nRESET
nINTR
nCS
N/C
BUSTMG
IN
OUT
IN
OUT
IN
nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
Hardware reset signal. Active Low.
Interrupt signal output. Active Low.
Chip Select input. Active Low.
Non-connection
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU and DMA
Timing.
L: High speed timing mode (only for non-multiplexed
bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
33
35
38
40
N/C
Power
Supply
Power
Supply
N/C
N/C
VDD
VDD
N/C
OUT
PWR
PWR
+3.3 volts power supply pins.
Non-connection
Revision 12-06-06
8
SMSC COM20020I 3.3V
DATASHEET
SMSC [ SMSC CORPORATION ]
