5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
4.0 DESCRIPTION OF PIN FUNCTIONS FOR TQFP
PIN NO
NAME
SYMBOL
I/O
DESCRIPTION
MICROCONTROLLER INTERFACE
44, 45,
46
Address
0-2
A0/nMUX
IN
IN
On a non-multiplexed mode, A0-A2 are address
input bits. (A0 is the LSB) On a multiplexed
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A1 is connected to an internal pull-up resistor.
A1
A2/ALE
IN
1, 2, 4,
7, 9, 10,
12, 13
Data 0-7
AD0-AD2,
D3-D7
I/O
On a non-multiplexed bus, these signals are used as
the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address lines
(latched by ALE) and as the low data lines. D3-D7
are always used for data only. These signals are
connected to internal pull-up resistors.
47, 48,
3, 5,
N/C
N/C
I/O
IN
Non-connection
14-17
37
nWrite/
nWR/DIR
nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
Direction
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
39
nRead/
nRD/nDS
IN
nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nData
Strobe
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
31
34
36
nReset In
nInterrupt
nRESET
nINTR
nCS
IN
OUT
IN
Hardware reset signal. Active Low.
Interrupt signal output. Active Low.
Chip Select input. Active Low.
nChip
Select
42
26
N/C
N/C
OUT
IN
Non-connection
Read/Write
Bus Timing
Select
BUSTMG
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU and DMA
Timing.
L: High speed timing mode (only for non-multiplexed
bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
33
35
N/C
N/C
OUT
Power
Supply
VDD
PWR
38
40
Power
Supply
VDD
N/C
PWR +3.3 volts power supply pins.
Non-connection
N/C
Revision 12-06-06
8
SMSC COM20020I 3.3V
DATASHEET
SMSC [ SMSC CORPORATION ]
