5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Note 6.1
(R/W) This bit can be Written or Read. For more information see Appendix C -
Identification of the COM20020 Rev B, Rev C and Rev D.
Software
Table 6.2 - Write Register Summary
ADDR
00
MSB
WRITE
EXCNAK
LSB
TA/
TTA
C0
REGISTER
NEW
INTERRUPT
MASK
RECON
RI/TR1
0
0
0
NEXTID
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
01
02
C7
C6
AUTO-
INC
C5
0
C4
0
C3
0
C2
C1
A9
RD-
DATA
A10
A8
03
A7
A6
A5
A4
A3
A2
A1
A0
04
05
D7
D6
0
D5
0
D4
0
D3
D2
D1
D0
(R/W)
(R/W)
SUB-
AD2
SUB-
AD1
SUB-
AD0
SUB-
AD0
TID0
NID0
SUBADR
Note 6.2
Note 6.2
06
RESET
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
TID2
SUB-
AD1
CONFIG-
URATION
TENTID
07-0
07-1
07-2
TID7
NID7
TID6
NID6
FOUR
NAKS
0
TID5
NID5
0
TID4
NID4
RCV-
ALL
TID3
NID3
CKP3
TID1
NID1
CKP1
NID2
NODEID
SETUP1
SLOW-
ARB
P1-
MODE
CKP2
07-3
07-4
0
0
0
0
0
0
0
TEST
RBUS-
TMG
0
CKUP1
CKUP0
EF
NO-
RCN-
TM1
RCN-
TM0
SETUP2
SYNC
Note 6.2
(R/W) This bit can be Written or Read. For more information see Appendix C -
Identification of the COM20020 Rev B, Rev C and Rev D.
Software
6.2
Internal Registers
The COM20020ID contains 14 internal registers. Table 6.1 and Table 6.2 illustrate the COM20020ID
register map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20020ID is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
SMSC COM20020I Rev D
Page 27
Revision 12-05-06
DATASHEET
SMSC [ SMSC CORPORATION ]
