5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
TABLE OF CONTENTS
2.0
3.0
4.0
5.0
5.1
5.2
5.3
5.4
5.5
5.6
6.0
6.1
6.2
7.0
7.1
7.2
7.3
7.4
7.5
7.6
8.0
8.1
8.2
9.0
10.0
11.0
12.0
12.1
GENERAL DESCRIPTION..............................................................................................................................5
PIN CONFIGURATIONS .................................................................................................................................6
DESCRIPTION OF PIN FUNCTIONS FOR TQFP ..........................................................................................8
PROTOCOL DESCRIPTION .........................................................................................................................11
N
ETWORK
P
ROTOCOL
..................................................................................................................................11
D
ATA
R
ATES
...............................................................................................................................................11
N
ETWORK
R
ECONFIGURATION
.......................................................................................................................12
B
ROADCAST
M
ESSAGES
...............................................................................................................................12
E
XTENDED
T
IMEOUT
F
UNCTION
.....................................................................................................................12
L
INE
P
ROTOCOL
..........................................................................................................................................13
SYSTEM DESCRIPTION...............................................................................................................................15
M
ICROCONTROLLER
I
NTERFACE
....................................................................................................................15
T
RANSMISSION
M
EDIA
I
NTERFACE
.................................................................................................................19
FUNCTIONAL DESCRIPTION ......................................................................................................................24
M
ICROSEQUENCER
......................................................................................................................................24
INTERNAL REGISTERS...........................................................................................................................25
I
NTERNAL
R
AM
............................................................................................................................................35
C
OMMAND
C
HAINING
....................................................................................................................................40
I
NITIALIZATION
S
EQUENCE
............................................................................................................................42
I
MPROVED
D
IAGNOSTICS
..............................................................................................................................42
OPERATIONAL DESCRIPTION ...................................................................................................................45
M
AXIMUM
G
UARANTEED
R
ATINGS
* ................................................................................................................45
D
C
E
LECTRICAL
C
HARACTERISTICS
...............................................................................................................45
TIMING DIAGRAMS......................................................................................................................................48
PACKAGE OUTLINES..................................................................................................................................60
APPENDIX A.................................................................................................................................................62
APPENDIX B.................................................................................................................................................65
S
OFTWARE
I
DENTIFICATION OF THE
COM20020I R
EV
B, R
EV
C
AND
R
EV
D .....................................................65
LIST OF FIGURES
Figure 1 - COM20020I OPERATION ...........................................................................................................................10
Figure 2 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...............................................16
Figure 3 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE......................................17
Figure 4 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE...............................................................................18
Figure 5 - COM20020I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS................................................20
Figure 6 - DIPULSE WAVEFORM FOR DATA OF 1-1-0 .............................................................................................20
Figure 7 - INTERNAL BLOCK DIAGRAM ....................................................................................................................22
Figure 8 – SEQUENTIAL ACCESS OPERATION........................................................................................................35
Figure 9 – RAM BUFFER PACKET CONFIGURATION ..............................................................................................38
Figure 10 - COMMAND CHAINING STATUS REGISTER QUEUE ...............................................................................40
Figure 11 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................48
Figure 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ..................................................49
Figure 13 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................50
SMSC COM20020I 3.3V
Page 3
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
