5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
PIN NO
24
NAME
nPulse 1
25
nPulse 2
28
29
Receive In
nTransmit
Enable
21
22
Crystal
Oscillator
8, 20,
32, 35,
38, 43
6, 11,
18, 23,
30, 41
3, 5,
14-17,
19, 27,
33, 40,
42, 48
Power
Supply
Ground
SYMBOL
I/O
DESCRIPTION
TRANSMISSION MEDIA INTERFACE
nPULSE1
OUT
In Normal Mode, these active low signals carry the
transmit data information, encoded in pulse format as
DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull or
nPULSE2
I/O
open-drain), while the nPULSE2 signal provides a
clock with frequency of doubled data rate. nPULSE1
is connected to a weak internal pull-up resistor on
the open/drain driver in backplane mode.
RXIN
IN
This signal carries the receive data information from
the line transceiver.
nTXEN
OUT
Transmission Enable signal. Active polarity is
programmable through the nPULSE2 pin.
nPULSE2 floating before power-up;
nTXEN active low
nPULSE2 grounded before power-up;
nTXEN active high (this option is only available in
Back Plane mode)
XTAL1
IN
An external crystal should be connected to these
pins. Oscillation frequency range is from 10 MHz to
XTAL2
OUT
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 with a 390ohm pull-up
resistor, and XTAL2 should be left floating.
VDD
PWR +5 Volt power supply pins.
VSS
PWR
Ground pins.
N/C
N/C
Non-connection
SMSC COM20020I 3.3V
Page 9
Revision 12-06-06
DATASHEET
SMSC [ SMSC CORPORATION ]
